1. Field of the Invention
The present invention relates to the field of digital computer systems, and more particularly, to the addressing of memory within a system which has two or more buses of different memory addressing capacities.
2. Description of Related Art
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus, providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, sound cards, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus.
A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa.
Many of the devices attached to the PCI bus and the ISA bus are master devices that can conduct processing independently of the bus or other devices. Certain devices coupled to the buses are considered to be slaves or targets that accept commands and respond to requests of a master. The PCI bus has an addressing capability of 32 bits to provide for 4 gigabytes of memory access. A master on the ISA bus can access a memory location in the memory on the PCI bus, although normally only within the lowest 16 megabyte region due to the 24-bit addressing of the ISA bus masters.
In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself.
In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is normally used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.
A commercially available DMA controller is the 8237 DMA controller manufactured by Intel. Each 8237 DMA controller provides four separate DMA channels which can be used independently for memory transfers. Certain well-known computer systems, such as the IBM PC/AT design, contain two 8237 DMA controllers. One channel of the first DMA controller is used to cascade the second DMA controller. The pair of DMA controllers therefore provide a total of seven DMA channels, with four channels provided by the first controller, and three channels provided by the second controller.
In the IBM PC/AT design, the lower order 16 bits of the memory address (15:0) are produced by the 8237 DMA controllers, and the upper 8 bits (23:16) are provided by a low page register that is loaded with values for the individual channels during programming of the DMA controllers. A prior art solution for addressing memory above the 16 megabyte limit uses external circuitry to set the most significant bit of a 32-bit PCI address high, when a master signal is detected on the ISA bus. This reallocated the 16 megabytes of memory to a different location within the 4 gigabytes of memory. However, all accesses to the memory on the PCI bus by the ISA bus masters would be to this same reallocated segment. There is therefore not a true addressability to the entire 4 gigabyte memory space by the ISA bus masters in the prior art system.
Another limitation of the prior art design of the IBM PC/AT DMA controller circuit is the boundary crossing limitation, which does not allow incrementing or decrementing across certain boundaries. For example if a boundary exists between bits 3 and 4 of an 8-bit byte (7:0), then if a first address is 00001111, an increment to a next address should cause a 1 to cross the boundary for a new address of 00010000. However, in the prior art arrangement, boundary crossings were not permitted. A boundary was normally present between the lower two bytes and the uppermost byte of the 24-bit memory address.
In addition to the memory address, another aspect of each DMA transfer is the transfer count, which indicates how large a transfer will be made. The prior art limits the transfer count to a 16 bit number, so that the largest possible transfer is a 64K byte block. This constraint hinders system performance since each transfer is limited to this size block, so that if a larger transfer is desired, it must be performed in separate 64K byte block transfers, with programming of the DMA controller needed for each transfer.